1. Field of the Invention
The present invention relates to a pulse density modulator, and more particularly, to a pulse density modulation (PDM) device employed in a portable telephone.
2. Description of the Related Art
There has been proposed a PDM device which performs a modulation process by changing a pulse density per unit time. This PDM device is provided in order to adjust the frequency of a pseudo noise (PN) code generated in a reception side of, for instance, a portable telephone of the code division multiple access (CDMA) system. By employing FIG. 1, the circuit constitution of a receiving system in such a portable telephone will be specifically described as follows.
A portable telephone 1 receives a transmission signal which is subjected to a spread spectrum modulation with a pseudo noise code and then transmitted, through an antenna 2, and inputs a reception signal S1 to a reception part 3. The reception part 3 performs a prescribed signal process such as a frequency conversion on the reception signal S1, and outputs a reception signal S2 thus obtained to a multiplier 4.
The multiplier 4 multiplies the reception signal S2 by a pseudo noise (PN) code S3 supplied from a pseudo noise (PN) code generator 5 (that is, an exclusive OR operation) in order to perform an inverse diffusion, and outputs a reception signal S4 thus obtained to a decoding part 6 and a frequency error correction block 7. The decoding part 6 performs a decoding process on the reception signal S4 in order to generate a baseband signal S5 and outputs the baseband signal S5 to a subsequent circuit (not shown).
The frequency error correction block 7 is designed to input the reception signal S4 to a frequency error detection part 8. The frequency error detection part 8 detects a frequency error between the reception signal S2 and the PN code S3 on the basis of the reception signal S4 which has been multiplied by the PN code S3, and outputs the resultant frequency error as frequency error data SE to a PDM part 9 corresponding to the above-described PDM device. The PDM part 9 performs a pulse density modulation on the frequency error data SE based on a clock signal S7 supplied from a frequency divider 10 in order to generate PDM waveform data SH, and outputs the PDM waveform data SH to a low-pass filter (LPF) 11.
The LPF 11 extracts a direct current component from the PDM waveform data SH to generate control voltage S9 and outputs the control voltage S9 to a voltage control crystal oscillator (VCXO) 12. The VCXO 12 generates a transmission signal S10 while changing a transmission frequency in accordance with the control voltage S9 supplied, and outputs the transmission signal S10 to the frequency divider 10. The frequency divider 10 divides the frequency of the transmission signal S10 in accordance with a predetermined number of frequency divisions so as to generate a clock signal S7, and outputs the clock signal S7 to the PN code generator 5 and the PDM part 9. The PN code generator 5 generates the PN code S3 based on the clock signal S7 supplied from the frequency divider 10 and outputs the PN code S3 to the multiplier 4.
The frequency error correction block 7 generates the clock signal S7 based on the reception signal S4 multiplied by the PN code S3, and supplies the clock signal S7 to the PN code generator 5. Thereby, the frequency of the PN code S3 generated in the PN code generator 5 is controlled so as to correspond to the frequency of the PN code at a transmission side included in the reception signal S2.
As illustrated in FIG. 2, the PDM part 9 comprises a count circuit 20, a basic waveform synthesis circuit 21 and a PDM waveform synthesis circuit 22. The PDM part 9 is designed to input the clock signal S7 supplied from the frequency divider 10 (FIG. 1) to the count circuit 20. The count circuit 20 composed of a binary count circuit of "n" bits, counts the clock signal S7 to generate count data SA of "n" bits and outputs the count data SA to the basic waveform synthesis circuit 21. In this case, the cycle of each bit forming the count data SA is composed of multiples of the cycle of the clock signal S7.
As shown in FIG. 3, the basic waveform synthesis circuit 21 outputs the least significant bit (LSB) data SA.sub.0 of the supplied count data SA of "n" bits as the most significant bit (MSB) data SB.sub.n-1 of basic waveform data to the PDM waveform synthesis circuit 22 as it is, while inputting the bit data SA.sub.0 to an inverter A.sub.0. Further, the basic waveform synthesis circuit 21 inputs bit data SA.sub.1 of a column one bit higher than the least significant bit of the count data SA, to an AND circuit B.sub.1 and an inverter A.sub.1. In the same way, the basic waveform synthesis circuit 21 is designed to input bit of the bit data SA to the corresponding AND circuits B and inverters A. In this connection, the basic waveform synthesis circuit 21 inputs the most significant bit data SA.sub.n-1 of the count data SA to an AND circuit B.sub.n-1.
The inverter A.sub.0 inverts the polarity of the bit data SA.sub.0 and outputs inverter output data SC.sub.0 thus obtained to the AND circuit B.sub.1 and an AND circuit C.sub.1. Further, the inverter A.sub.1 inverts the polarity of the bit data SA.sub.1 and outputs inverter output data SC.sub.1 thus obtained to the AND circuit C.sub.1. In the same way, the inverter A afterward inverts the polarity of the bit data SA and outputs inverter output data SC thus obtained to corresponding AND circuits C.
The AND circuit C.sub.1 takes the AND of the inverter output data SC.sub.0 obtained by inverting the polarity of the count data SA.sub.0 of the least significant bit and the inverter output data SC.sub.1 obtained by inverting the polarity of the bit data SA.sub.1 of a column one bit higher than the least significant bit, and then outputs AND output data SD.sub.1 thus obtained to an AND circuit B.sub.2 and an AND circuit C.sub.2 (not shown). In the same way, the AND circuit C afterward takes the AND of AND output data SD outputted from the AND circuit C of a column one bit lower than that of it and inverter output data SC outputted from the inverter A, and then outputs AND output data SD thus obtained to the AND circuit B and the AND circuit C of a column one bit higher than that of it. In this connection, an AND circuit C.sub.n-2 takes the AND of AND output data SD.sub.n-3 outputted from an AND circuit C.sub.n-3 and inverter output data SC.sub.n-2 outputted from an inverter A.sub.n-2, and outputs AND output data SD.sub.n-2 thus obtained to the AND circuit B.sub.n-1.
The AND circuit B.sub.1 takes the AND of the inverter output data SC.sub.0 and the bit data SA.sub.1, and outputs the computed result to the PDM waveform synthesis circuit 22 as bit data SB.sub.n-2 of a column one bit lower than the most significant bit of the basic waveform data. In addition, the AND circuit B.sub.2 takes the AND of the AND output data SD.sub.1 and count data SA.sub.2, and outputs the computed result to the PDM waveform synthesis circuit 22 as bit data SB.sub.n-3 of a column two bits lower than the most significant bit. In such a way, the AND circuit B takes the AND of the AND output data SD and the count data SA, and outputs the computed result to the PDM waveform synthesis circuit 22 as basic waveform data SB of a desired column.
As shown in FIG. 4, the PDM waveform synthesis circuit 22 inputs the the least significant bit data SB.sub.0 of the basic waveform data SB to an AND circuit D.sub.0, and inputs the bit data SB.sub.1 of a column one bit higher than the least significant bit to an AND circuit D.sub.1. In this manner, the PDM waveform synthesis circuit 22 inputs the bits of the basic waveform data SB to corresponding AND circuits D.
The PDM waveform synthesis circuit 22 is supplied the frequency error data SE from the frequency error detection part 8. The PDM waveform synthesis circuit 22 inputs the least significant bit data SE.sub.0 of the frequency error data SE to the AND circuit D.sub.0, and inputs bit data SE.sub.1 of a column one bit higher than the least significant bit to the AND circuit D.sub.1. In the same way, the PDM waveform synthesis circuit 22 afterward inputs the frequency error data SE to the corresponding AND circuits D.
The AND circuit D.sub.0 takes the AND of the least significant bit data SB.sub.0 of the basic waveform data SB and the bit data SE.sub.0 of the frequency error data SE, and outputs AND output data SF.sub.0 to an OR circuit E.sub.0. On the other hand, the AND circuit D.sub.1 takes the AND of the bit data SB.sub.1 of a column one bit higher than the least significant bit and the bit data SE.sub.1, and outputs AND output data SF.sub.1 thus obtained to the OR circuit E.sub.0. In the same way, the AND circuit D afterward takes the AND of bit data of a desired column of the basic waveform data SB and bit data of the frequency error data SE, and outputs AND output data SF thus obtained to the corresponding OR circuits E.
The OR circuit E.sub.0 takes the OR of the AND output data SF.sub.0 obtained from the AND of the least significant bits and the AND output data SF.sub.1 obtained from the AND of the columns one bit higher than the least significant bits, and outputs OR output data SG.sub.0 thus obtained to an OR circuit E.sub.1. The OR circuit E.sub.1 takes the OR of the OR output data SG.sub.0 and AND output data SF.sub.2 outputted from an AND circuit D.sub.2 (not shown), and outputs OR output data SG.sub.1 thus obtained to an OR circuit E.sub.2 (not shown). In the same way, the OR circuit E takes the OR of OR output data SG outputted from the OR circuit E of a one bit lower column and the AND output data SF, and outputs OR output data SG thus obtained to an OR circuit E of a one bit higher column. In such a way, the PDM waveform synthesis circuit 22 takes the AND of the basic waveform data SB and the frequency error data SE, takes the OR of the AND output data SF thus obtained so as to generate the PDM waveform data SH, and outputs the PDM waveform data SH to the LPF 11 (FIG. 1).
In the portable telephone 1, the frequency of the transmission signal S10 generated in the VCXO 12 is divided according to a predetermined number of frequency divisions so that the clock signal S7 is generated for controlling a digital processing system circuit such as the PDM part 9. Further, the frequency of the transmission signal S10 is divided according to a different number of frequency divisions so that a clock signal is generated for controlling an analog processing system circuit such as the reception part 3. Therefore, it is desirable that the frequency of the transmission signal S10 generated in the VCXO 12 is selected so as to be the least common multiple of the frequency of the clock signal S7 employed in the digital processing system circuit and the frequency of the clock signal employed in the analog processing system circuit.
However, when it is intended to form a transmission signal having the frequency of the least common multiple of the frequency of the clock signal S7 employed in the digital processing system circuit and the frequency of the clock signal employed in the analog processing system circuit, a transmission signal having the very high frequency needs to be generated. In practice, it is extremely difficult to generate such a transmission signal. Accordingly, the VCXO 12 is designed to generate, for example, the transmission signal S10 which has a predetermined times as high a frequency as the frequency of the clock signal employed in the analog processing system circuit. Therefore, it is possible that the frequency of the transmission signal S10 is not a multiple of the frequency of the clock signal used in the digital processing system circuit. Accordingly, since the frequency divider 10 cannot divide the frequency of the transmission signal S10 according to the same by an equal cycle (hereinafter, referred to as an equal frequency division), it is possible that the frequency divider 10 cannot help generating the clock signal S7 including a clock whose cycle is different from that of other clocks (hereinafter, referred to as an unequal cycle component).
Thus, referring to FIGS. 5 to 8, a case in which the clock signal S7 including the unequal cycle component is inputted to the PDM part 9 is explained. For instance, as illustrated in FIG. 5A, it is assumed that the clock signal S7 to be inputted to the count circuit 20 of "3" bits is slowed before the rise timings of the "fourth", the "sixth" and the "eighth" clocks of its "one" cycle.
The count circuit 20 counts up the clocks synchronizing with the rise timing of the clock so as to generate the count data SA of "3" bits, and outputs the count data SA to the basic waveform synthesis circuit 21. At this time, the count circuit 20 counts up the clock signal S7 so as to generate the least significant bit data SA.sub.0 which is obtained by applying a "1/2" frequency division to the frequency of the clock signal S7 (FIG. 5B). Further, the count circuit 20 generates the bit data SA.sub.1 of a column one bit higher than the least significant bit (FIG. 5C), which is obtained by applying a "1/4" frequency division to the frequency of the clock signal S7. Further, the count circuit 20 generates the bit data SA.sub.2 of the most significant bit which is obtained by applying a "1/8" frequency division to the frequency of the clock signal S7 (FIG. 5D).
Subsequently, referring to FIGS. 6A to 6D, the basic waveform data SB.sub.0 to SB.sub.2 outputted from the basic waveform synthesis circuit 21 is explained. First of all, FIG. 6A shows the clock signal S7 inputted to the count circuit 20. The basic waveform synthesis circuit 21 generates the least significant bit data SB.sub.0 which indicates a logical level "H" in the phase where the bit data SA.sub.2 of the count data SA indicates the logical level "H" and the bit data SA.sub.0 and SA.sub.1 indicate a logical level "L". Then, the basic waveform synthesis circuit 21 outputs the bit data SB.sub.0 to the PDM waveform synthesis circuit 22 (FIG. 6B).
In addition, the basic waveform synthesis circuit 21 generates the bit data SB.sub.1 of a column one bit higher than the least significant bit which indicates the logical level "H" in the phase where the bit data SA.sub.1 indicates the logical level "H" and the bit data SA.sub.0 indicates the logical level "L". Then, the basic waveform synthesis circuit 21 outputs the bit data SB.sub.1 to the PDM waveform synthesis circuit 22 (FIG. 6C). Further, the basic waveform synthesis circuit 21 directly outputs the count data SA.sub.0 to the PDM waveform synthesis circuit 22 as the basic waveform data SB.sub.2 of the most significant bit as it is (FIG. 6D).
The time ratio of the logical level "H" and the logical level "L" in the basic waveform data SB generated in such a manner is "3/19" in the case of the least significant bit data SB.sub.0 of the basic waveform data SB. In the case of the bit data SB.sub.1 of a column one bit higher than the least significant bit, the time ratio is "6/19". In the case of the bit data SB.sub.2 of the most significant bit, the time ratio is "8/19". Note that, phases of the bit data SB.sub.0 to SB.sub.2 are not superposed in the logical level "H" each other.
Next, referring to FIGS. 7A to 7I, the PDM waveform data SR outputted from the PDM waveform synthesis circuit 22 is explained. First of all, FIG. 7A shows the clock signal S7 inputted to the count circuit 20. The PDM waveform synthesis circuit 22 takes the AND of the frequency error data SE supplied from the frequency error detection part 8 and the basic waveform data SB, then takes the OR thereof to generate the PDM waveform data SH and outputs the PDM waveform data SH to the LPF 11 (FIG. 1).
When the frequency error data SE is "000", the PDM waveform synthesis circuit 22 outputs a logical level "0" as PDM waveform data SH.sub.0 of a waveform number "0" (FIG. 7B). Further, when the frequency error data SE is "001", the PDM waveform synthesis circuit 22 outputs the least significant bit data SB.sub.0 to the LPF 11 (FIG. 1) as PDM waveform data SH.sub.1 of a waveform number "1" (FIG. 7C). Furthermore, when the frequency error data SE is "010", the PDM waveform synthesis circuit 22 outputs the basic waveform synthetic data SB.sub.1 of a column one bit higher than the least significant bit as PDM waveform data SH.sub.2 of a waveform number "2" (FIG. 7D).
In the next place, when the frequency error data SE is "011", the PDM waveform synthesis circuit 22 synthesizes the least significant bit data SB.sub.0 of the basic waveform synthetic data and the bit data SB.sub.1 of a column one bit higher than the least significant bit and then outputs data thus obtained as PDM waveform data SH.sub.3 of a waveform number "3" (FIG. 7E). Further, when the frequency error data SE is "100", the PDM waveform synthesis circuit 22 outputs the most significant bit data SB.sub.2 as PDM waveform data SH.sub.4 of a waveform number "4" (FIG. 7F). Furthermore, when the frequency error data SE is "101", the PDM waveform synthesis circuit 22 synthesizes the least significant bit data SB.sub.0 and the most significant bit data SB.sub.2 and then outputs data thus obtained as PDM waveform data SH.sub.5 of a waveform number "5" (FIG. 7G).
Similarly, when the frequency error data SE is "110", the PDM waveform synthesis circuit 22 synthesizes the bit data SB.sub.1 of a column one bit higher than the least significant bit and the most significant bit data SB.sub.2 and then outputs data thus obtained as PDM waveform data SH.sub.6 of a waveform number "6" (FIG. 7H). Further, when the frequency error data SE is "111", the PDM waveform synthesis circuit 22 completely synthesizes the bit data SB.sub.0, the bit data SB.sub.1 and the bit data SB.sub.2 of the basic waveform synthetic data SB and then outputs data thus obtained as PDM waveform data SH.sub.7 of a waveform number "7" (FIG. 7I).
The LPF 11 extracts the direct current component from the PDM waveform data SH generated in the PDM part 9, and thereby generates the control voltage S9 of a desired voltage level corresponding to the PDM waveform data SH and outputs the control voltage to the VCXO 12.
Now, the relation between the PDM waveform data SH and the control voltage S9 is explained with reference to FIG. 8. The control voltage S9 increases linearly within a range of the PDM waveform data SH.sub.0 to SH.sub.3 of the waveform numbers "0" to "3". At the time of the PDM waveform data SH.sub.4 of the waveform number "4", the control voltage S9 temporarily decreases. After that, the control voltage S9 increases linearly within a range of the PDM waveform data SH.sub.4 to SH.sub.7 of the waveform numbers "4" to "7" again. That is to say, the control voltage S9 increases linearly until the frequency error data SE undergoes an increment to "011", starting from "000". However, when the frequency error data SE undergoes an increment process to "100", the control voltage S9 decreases temporarily. The control voltage S9 apparently increases again until the frequency error data SE is subjected to the increment process from "100" to "111".
As mentioned above, when the clock signal S7 including the unequal cycle component is supplied to the PDM part 9, since the linearity is not established between the waveform number of the PDM waveform data SH and the control voltage S9, there is a problem that the VCXO 12 can not be controlled with accuracy.